The present invention generally relates to semiconductor devices, and more particularly, to bipolar complementary metal-oxide-semiconductor (BiCMOS) devices.
Complementary metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FETs) as part of advanced integrated circuits (IC), such as CPUs, memory, storage devices, and the like. At the core of planar FETs, a channel region is formed in an N-doped or P-doped semiconductor substrate on which a gate structure is formed. The overall fabrication process includes forming a gate structure over a channel region connecting a source-drain region within the substrate on opposite ends of the gate, typically with some vertical overlap between the gate and the source and drain region.
Bipolar junction transistor (BJT) technology may be typically found in demanding types of integrated circuits, especially integrated circuits for high-frequency applications. One high-frequency application for BJTs is in radiofrequency integrated circuits (RFICs), which are used in wireless communications systems, power amplifiers in cellular telephones, and other types of high speed integrated circuits. Conventional BJTs are three-terminal electronic devices that include three semiconductor regions, namely an emitter, a base, and a collector. Generally, a BJT includes a pair of p-n junctions, namely a collector-base junction and an emitter-base junction. A voltage applied across the emitter-base junction of a BJT controls the movement of charge carriers that produce charge flow between the collector and emitter regions of the BJT.
An NPN bipolar junction transistor includes two regions of N-type semiconductor material constituting the emitter and collector, and a region of P-type semiconductor material located between the two regions of n-type semiconductor material to constitute the base. A PNP bipolar junction transistor has two regions of P-type semiconductor material constituting the emitter and collector, and a region of N-type semiconductor material located between two regions of P-type semiconductor material to constitute the base.
BJTs may also be combined with CMOS field effect transistors in bipolar complementary metal-oxide-semiconductor (BiCMOS) integrated circuits, which take advantage of the positive characteristics of both transistor types in the construction of the integrated circuit.
Scaling down of CMOS FETs dimensions requires a high-k metal gate to reduce gate leakage and improve device performance. A polycrystalline silicon material, commonly referred as polysilicon or poly, is normally used in the gate manufacturing process. Polysilicon exhibits high thermal resistivity, which makes a polysilicon gate resistant to high temperature processes such as high temperature annealing. The replacement of a polysilicon gate with a metal gate electrode is frequently used in CMOS fabrication to address problems related to high temperature processing on metal materials. This process is known as replacement metal gate (RMG) or gate last process. A RMG process includes the formation of a dummy polysilicon gate structure, commonly referred to as a dummy poly gate or simply a dummy gate, in the semiconductor substrate. The device manufacturing may continue until deposition of an interlayer dielectric (ILD) layer. After the ILD layer deposition, the dummy gate may be removed and replaced with a high-k metal gate.
Improved RMG processes integrating BiCMOS transistor technology may facilitate advancing the capabilities of current high-k device technology.